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PRELIMINARY
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
* 25 ns and 45 ns Access Times * "Hands-off" Automatic STORE on Power Down with external 68F capacitor * STORE to QuantumTrap(R) Nonvolatile Elements is initiated by Software, Hardware or Autostore(R) on Power-down * RECALL to SRAM Initiated by Software or Power-up * Infinite READ, WRITE and RECALL Cycles * 15 mA Typical ICC at 200 ns Cycle Time * 1,000,000 STORE Cycles to QuantumTrap * 100-Year Data Retention to QuantumTrap * Single 5V Operation +10% * Commercial Temperature * SOIC Package * RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides Infinite read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
Quantum Trap 512 X 512
A5 A6 A7 A8 A9 A 11 A 12 A 13 A 14
VCC
VCAP
STORE
POWER CONTROL STORE/ RECALL CONTROL
ROW DECODER
STATIC RAM ARRAY 512 X 512
RECALL
HSB
SOFTWARE DETECT COLUMN I/O
A13 - A 0
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
INPUT BUFFERS
DQ 1
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
OE
CE WE
Cypress Semiconductor Corporation Document #: 001-06968 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 28, 2006
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PRELIMINARY
Pin Configurations
CY14E256L
V CAP A 14 A 12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
V CC HSB
WE
A 13 A8 A9 A 11 OE NC A 10 CE DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
32 - Lead SOIC
Top View
(Not To Scale)
26 25 24 23 22 21 20 19 18 17
Pin Definitions
Pin Name A0-A14 WE CE OE VSS VCC HSB I/O Type Input Input Input Input Ground Description Address Inputs used to select one of the 32,768 bytes of the nvSRAM. Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to the address location latched by the falling edge of CE. Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tri-state. Ground for the device. Should be connected to ground of the system.
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
Power Supply Power Supply inputs to the device. Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected. (Connection Optional) Power Supply Autostore(R) Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connects. This pin is not connected to the die.
VCAP NC
Document #: 001-06968 Rev. *C
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PRELIMINARY
Device Operation
The CY14E256L nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The CY14E256L supports Infinite reads and writes just like a typical SRAM. In addition, it provides Infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations.
CY14E256L
A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 1 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC Characteristics table for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull-up should be placed on WE to hold it inactive during power-up.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and OE are low while WE and HSB are high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAA (READ cycle #1). If the READ is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and will remain valid until another address change or until CE or OE is brought high, or WE or HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common I/O pins I/O0-7 will be written into the memory if it is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. It is recommended that OE be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left low, internal circuitry will turn off the output buffers tHZWE after WE goes low.
Figure 1. AutoStore(R) Mode
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store, activated by HSB, Software Store, activated by an address sequence, and AutoStore, on device power down. AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E256L. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC.
Figure 2. System Power Mode
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PRELIMINARY
In system power mode (Figure 2), both VCC and VCAP are connected to the +5V power supply without the 68-F capacitor. In this mode the AutoStore function of the CY14E256L will operate on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10-ms STORE cycle. If an automatic STORE on power loss is not required, then VCC can be tied to ground and + 5V applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the CY14E256L is operated in this configuration, references to VCC should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered through software control or the HSB pin. It is not permissible to change between these three options "on the fly".
CY14E256L
tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple CY14E256L while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other CY14E256L. An external pull-up resistor to +5V is required since HSB acts as an open-drain pull-down. The VCAP pins from the other CY14E256L parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the CY14E256L detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those CY14E256L that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the CY14E256L will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY14E256L will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected.
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete. If the CY14E256L is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10-Kohm resistor should be connected either between WE and system VCC or between CE and system VCC. Figure 3. AutoStore Inhibit Mode To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. (In the above Figures 1, 2 and 3 * indicates that If HSB is not used, it should be left unconnected.)
Software STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14E256L software STORE cycle is initiated by executing sequential CE-controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle
Hardware STORE (HSB) Operation
The CY14E256L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the CY14E256L will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open-drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY14E256L will continue SRAM operations for
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PRELIMINARY
The software sequence may be clocked with CE-controlled READs or OE-controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that OE be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
CY14E256L
Software RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE-controlled READ operations must be performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements.
Figure 4. Current vs. Cycle Time (READ)
Figure 5. Current vs. Cycle Time (WRITE) ICC and READ/WRITE cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable).Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14E256L depends on the following items: 1. The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. CMOS vs. TTL Input Levels. 5. The operating temperature. 6. The VCC level. 7. I/O loading.
Data Protection
The CY14E256L protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14E256L is in a WRITE mode (both CE and WE low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power-up or brown-out conditions.
Noise Considerations
The CY14E256L is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
Preventing STOREs
The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20 s at the onset of a STORE. When the CY14E256L is connected for AutoStore operation (system VCC connected to VCC and a 68-F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY14E256L will attempt to pull HSB low; if HSB doesn't actually get below VIL,the part will stop trying to pull HSB low and abort the STORE attempt.
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between Table 1. Hardware Mode Selection CE H L L X WE X H L X HSB H H H L A13-A0 X X X X
Mode Not Selected Read SRAM Write SRAM Nonvolatile STORE
I/O Output High-Z Output Data Input Data Output High-Z
Power Standby Active Active ICC2 Page 5 of 16
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Document #: 001-06968 Rev. *C
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND.......... -0.5V to 7.0V Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Input Voltage ............................................ -0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential...................-2.0V to VCC + 2.0V
CY14E256L
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [1] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 4.5V to 5.5V
DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V) [2]
Parameter ICC1 Description Average VCC Current Test Conditions tRC = 25 ns Commercial tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0mA. All Inputs Don't Care, VCC = Max. Average current for duration tSTORE Min. Max. 97 70 Unit mA mA mA mA mA
ICC2 ICC3
Average VCC Current during STORE
3 15
Average VCC Current at WE > (VCC - 0.2). All other inputs cycling. tAVAV = 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained 25C typical without output loads. Average VCAP Current All Inputs Don't Care, VCC = Max. during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0MHz. -1 -5 2.2 VSS - 0.5 IOUT = -2 mA IOUT = 4 mA 2.4
ICC4 ISB
2 1.5
mA mA
IIX IOZ VIH VIL VOH VOL
Input Leakage Current VCC = Max., VSS < VIN < VCC Off-State Output VCC = Max., VSS < VIN < VCC, Leakage Current CE or OE > VIH Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage
+1 +5 VCC + 0.5 0.8 0.4
A A V V V V
Capacitance [3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max. 5 7 Unit pF pF
Notes: 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 5V. Not 100% tested. 3. These parameters are guaranteed but not tested.
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PRELIMINARY
Thermal Resistance [3]
Parameter Description Test Conditions
CY14E256L
32-SOIC TBD TBD Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test methods and procedures (Junction to Ambient) for measuring thermal impedance, per EIA / JESD51. Thermal Resistance (Junction to Case)
AC Test Loads
R1 480 5.0V OUTPUT 30 pF R2 255
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V
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PRELIMINARY
AC Switching Characteristics
Parameter Cypress Alt. Parameter Parameter SRAM Read Cycle tACE tRC [4] tAA
[5]
CY14E256L
25ns part 45ns part Min. Max. 45 45 25 10 5 5 10 0 10 0 25 25 20 20 10 0 20 0 0 10 5 5 45 30 30 15 0 30 0 0 14 0 45 0 15 5 5 15 45 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Set-Up to End of Write Data Hold After End of Write Address Set-Up to End of Write Address Set-Up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write
Min.
Max. 25
tACS tRC tAA tOE
[5]
25
tDOE tOHA tLZCE [6] tHZCE [6] tLZOE tHZOE tPU[ 3] tPD [3] tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE
[6,7] [6] [6]
tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
SRAM Write Cycle
tLZWE [6]
AutoStore/Power-Up RECALL
CY14E256L Parameter tHRECALL tSTORE [9] VSWITCH tVCCRISE
[8]
Description Power-Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time
Min.
Max. 550 10
Unit s ms V s
4.0 150
4.5
Notes: 4. WE must be HIGH during SRAM Read Cycles. 5. Device is continuously selected with CE and OE both Low. 6. Measured 200mV from steady state output voltage. 7. If WE is Low when CE goes Low, the outputs remain in the high-impedance state. 8. tHRECALL starts from the time VCC rises above VSWITCH. 9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place.
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PRELIMINARY
Software Controlled STORE/RECALL Cycle [10,11]
25ns part Parameter tRC tAS tCW tGLAX tRECALL Address Set-Up Time Clock Pulse Width Address Hold Time RECALL Duration Description STORE/RECALL Initiation Cycle Time Min. 25 0 20 20 20 Max.
CY14E256L
45ns part Min. 45 0 30 20 20 Max. Unit ns ns ns ns s
Hardware STORE Cycle
CY14E256L Parameter tSTORE
[6]
Description STORE Cycle Duration Time allowed to complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
Min 1
Max 10 700
Unit ms s ns ns ns
tDELAY [12] tRESTORE tHLHX tHLBL
[13]
15 300
Switching Waveforms
tRC
ADDRESS
t AA t OH
DQ (DATA OUT) DATA VALID
Figure 6. SRAM Read Cycle #1: Address Controlled [4, 5, 14]
Notes: 10. The software sequence is clocked with CE controlled READs. 11. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. 12. Read and Write cycles in progress before HSB are given this amount of time to complete. 13. tRESTOREis only applicable after tSTORE is complete. 14. HSB must remain HIGH during READ and WRITE cycles.
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PRELIMINARY
Switching Waveforms (continued)
tRC
ADDRESS
CY14E256L
CE
tLZCE
tACE
tPD tHZCE
OE
DQ (DATA OUT)
tLZOE t PU
tDOE
DATA VALID
tHZOE
ACTIVE
ICC
STANDBY
Figure 7. SRAM Read Cycle #2: CE Controlled [4,14]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 8. SRAM Write Cycle #1: WE Controlled [14,15]
Note: 15. CE or WE must be > VIH during address transitions.
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PRELIMINARY
Switching Waveforms (continued)
CY14E256L
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Figure 9. SRAM Write Cycle #2: CE Controlled
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PRELIMINARY
Switching Waveforms (continued)
CY14E256L
VCC VSWITCH VRESET
AutoStore
POWER-UP RECALL
tRESTORE
HSB
tVSBL tDELAY
tSTORE
DQ (DATA OUT)
POWER UP RECALL
(NO SRAM WRITES)
BROWN OUT NO STROKE
BROWN OUT AutoStore TM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStore TM RECALL WHEN VCC RETURNS ABOVE VSWITCH
NO RECALL (VCC DID NOT GO BELOW VRESET)
Figure 10. AutoStore/Power-Up RECALL
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PRELIMINARY
Switching Waveforms (continued)
tRC
ADDRESS ADDRESS # 1
CY14E256L
tRC
ADDRESS # 6
tSA
CE
tSCE
tGLAX
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Figure 11. CE-controlled Software STORE/RECALL Cycle [11]
HSB (IN)
tHLHX tSTORE
HIGH IMPEDANCE
HSB (OUT)
tHLBL
HIGH IMPEDANCE
t DELAY
DQ (DATA OUT) DATA VALID DATA VALID
Figure 12. Hardware STORE Cycle
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PRELIMINARY
PART NUMBERING NOMENCLATURE CY 14 E 256 L- SZ 25 X C T
Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70C)
CY14E256L
Pb-Free
Package: SZ - 32 SOIC Data Bus: L - x8 Density: 256 - 256 Kb Voltage: E - 5.0V NVSRAM 14 - AutoStore + Software Store + Hardware Store
Speed: 25 - 25 ns 45 - 45 ns
Cypress
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PRELIMINARY
Ordering Information
Speed (ns) 25 45 Ordering Code CY14E256L-SZ25XCT CY14E256L-SZ45XCT Package Diagram 51-85127 51-85127 Package Type 32-pin SOIC (Pb-Free) 32-pin SOIC (Pb-Free)
CY14E256L
Operating Range Commercial Commercial
Package Diagrams
32-pin (300-Mil) SOIC (51-85127)
PIN 1 ID
16 1
0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642]
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119
MIN. MAX.
17
32
PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG.
SEATING PLANE
0.810[20.574] 0.822[20.878]
0.090[2.286] 0.100[2.540]
0.004[0.101] 0.050[1.270] TYP. 0.014[0.355] 0.020[0.508] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] 0.021[0.533] 0.041[1.041] 0.006[0.152] 0.012[0.304]
51-85127-*A
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation.All products and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY14E256L 256-Kbit (32K x 8) nvSRAM Document Number: 001-06968 REV. ** *A *B *C ECN NO. 427789 437321 472053 503290 Issue Date See ECN See ECN See ECN See ECN Orig. of Change TUP TUP TUP PCI New Data Sheet Show Data Sheet on external Web Description of Change
CY14E256L
Updated Part Numbering Nomenclature and Ordering Information Changed from "Advance" to "Preliminary" Changed the term "Unlimited" to "Infinite" Changed ICC3 value from 10mA to 15mA Removed Industrial Grade mention Removed 35ns speed bin Removed Icc1 values from the DC table for 35 ns Industrial Grade Corrected VIL min. spec from (VCC - 0.5) to (VSS - 0.5) Removed all references pertaining to OE controlled "Software STORE and RECALL" operation Changed the address locations of the software STORE/RECALL command Updated "Part Nomenclature Table" and "Ordering InformationTable"
Document #: 001-06968 Rev. *C
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